EMBEDDED SOC USING HIGH PERFORMANCE ARM CORE PROCESSOR

Embedded soc using high performance arm core processor

  IJCOT-book-cover
 		 International Journal of Computer & Organization Trends (IJCOT)          
 
© 2011 by IJCOT Journal
Volume-1 Issue-1                          
Year of Publication : 2011
Authors : D.sridhar raja

Citation

D.sridhar raja "Embedded soc using high performance arm core processor", International Journal of Computer & organization Trends  (IJCOT), V1(1):1-5 July - August 2011, ISSN 2249-2593, www.ijcotjournal.org. Published by Seventh Sense Research Group. 

Abstract

ARM is one of the most licensed and thus widespread processor cores in the world. Used especially in portable devices due to low power consumption and reasonable performance. The ARM processor core is a leading processor design for the embedded domain. In the embedded domain, both memory and energy are important concerns. For this reason the 32 bit ARM processor also supports the 16 bit Thumb instruction set. For a given program, typically the Thumb code is smaller than the ARM code. Therefore by using Thumb code the I-cache activity, and hence the energy consumed by the I-cache, can be reduced. However, the limitations of the Thumb instruction set, in comparison to the ARM instruction set, can often lead to generation of poorer quality code. Thus, while Thumb code may be smaller than ARM code, it may perform poorly and thus may not lead to overall energy savings. We present a comparative evaluation of ARM and Thumb code to establish the above claims and present analysis of Thumb instruction set restrictions that lead to the loss of performance. We propose profile guided algorithms for generating mixed ARM and Thumb code for application programs so that the resulting code gives significant code size reductions without loss in performance. Our experiments show that this approach is successful and in fact in some cases the mixed code outperforms both ARM and Thumb code. This ARM processor is designed using pipelined architecture; through this we can improve the speed of the operation. In this we are using 5-stage pipelining. The 5 stages are Fetch, Decode, Execute, Memory and Write Back. During the design process we are including varies low power techniques in architectural level also we are proved that our proposed methods is more efficient than Back-end low power reduction techniques.

References

[1] A 32-bit RISC core for embedded application “Sung Ho Kwak, Seung Ho Lee, Byeong Yoon Choi, Moon Key Lee”
[2] ARM system on chip architecture “steve Furber”.
[3] ARM system developers guide “Andrew N Sloss, Dominic Symes, Chris Wright”.
[4] Reuse methodology manual for SOC designs “Michael keating and Pierre Bricaud”.
[5]Synthesis and Optimization of DSP algorithms “George A Constantinides, Peter Y. K Cheung and Wayne Luk”.
[6] ARM architecture Reference manual.

Keywords

Architectural level power reduction, High speed architecture, Micro architecture, Common power format.