Improved Design of Low Power TPG Using LP-LFSR

International Journal of Computer & Organization Trends  (IJCOT)          
© 2013 by IJCOT Journal
Volume-3 Issue-2                          
Year of Publication :  2013
Authors :  Praveen Kasunde, Dr. K B ShivaKumar, Dr. M Z Kurian


   Praveen Kasunde, Dr. K B ShivaKumar, Dr. M Z Kurian     "Improved Design of Low Power TPG Using LP-LFSR" . International Journal of Computer & organization Trends  (IJCOT), V3(2):27-31 Mar - Apr 2013, ISSN:2249-2593, Published by Seventh Sense Research Group.


This paper presents a novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The purpose of the BIST is to reduce power dissipation without affecting the fault coverage. The demonstrated test pattern generator reduces the switching activity among the test patterns at the most. In this method, the single input change patterns generated by a counter and a gray code generator are Exclusive–ORed with the seed generated by the low power linear feedback shift register [LP-LFSR]. The proposed scheme is evaluated by using a 4x4 Braun array multiplier. The System-On-Chip (SOC) approach is adopted for implementation on Altera Field Programmable Gate Arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.


[1] A.Kavitha, G.Seetharaman, T.N.Prabhakar and Shrinithi.S “Design of Low Power TPG Using LP-LFSR”, 2012 third international conference on intelligent systems modeling and simulation.
[2] BalwinderSingh, Arun khosla and Sukhleen Bindra “Power Optimization of linear feedback shift register(LFSR) for low power BIST”, 2009 IEEE international Advance computing conference(IACC 2009) Patiala,India 6-7 March 2009.
[3] Y.Zorian, “A Distributed BIST control scheme for complex VLSI devices,” Proc. VLSI Test Symp., P.4-9,1993.
[4] P.Girard, ”survey of low-power testing of VLSI circuits,” IEEE design and test of computers, Vol. 19,no.3,PP 80-90,May-June 2002.
[5] Mechrdad Nourani, ”Low-transition test pattern generation for BIST- Based Applications”, IEEE TRANSACTIONS ON COMPUTERS, Vol 57,No.3 ,March 2008.
[6] P.Girard, L.Guiller, C.Landrault, S.Pravossoudovitch,and H.J.Wunderlich, ” A modified clock scheme for a low power BIST test pattern generator,” 19th IEEE proc. VLSI test Symp.,CA,pp-306- 311,Apr-May 2001.
[7] S.Wang and S.K.Gupta, ”DS-LFSR: a BIST TPG for low switching activity,” IEEE design of Integrated circuits and systems, Vol. 21,No.7,pp.842-851,July 2002.
[8] I.Voyiatzis,A.paschalis,D.Nikolos and C.Halatsis, ”An efficient built-in self test method for robust path delay fault testing,” Journal of electronic testing: Theory and applications Vol.8,No.2,pp-219-222,Apr- 1996.
[9] S.C.Lei, J.Guo, L.Cao, Z.Ye.Liu, and X.M.Wang, ”SACSR: A low power BIST method for sequential circuits”, Academic Journal of XI’AN jiaotong university(English Edition),Vol.20,no.3,pp.155-159,2008.
[10] R.H.He,X.W.Li and Y.Z.Gong, ” A scheme for low power BIST test pattern generator”, micro electronics & computer,no.2,pp.36-39 Feb.2003.
[11] BOYE and Tian-Wang Li, ”A novel BIST scheme for low power testing”, 2010 IEEE.
[12] R.S.Katti,X.Y.Ruan , and H.Khattri, ”Multiple-Output Low-Power Linear feedback shift register design”, IEEE Trans.circuitsSyst.I,Vol.53,No.7,pp-1487-1495,July 2006.
[13] S.C. Lei, X.Y.Hou ,Z.B.Shao and F.Liang, ”A class of SIC circuits: theory and application in BIST design”, IEEE trans. circuits syst. II, vol.55,no.2,pp.161-165,Feb.2008.


FPGA, BIST, LP-LFSR, Switching activity.