Redundancy Efficient Crosstalk Avoidance Scheme in VLSI Circuits
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International Journal of Computer & Organization Trends (IJCOT) | 
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| © 2013 by IJCOT Journal | ||
| Volume-3 Issue-2 |
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| Year of Publication : 2013 | ||
| Authors : Dr. K. Padmapriya , D. Gopinadh |
Citation
Dr. K. Padmapriya , D. Gopinadh "Redundancy Efficient Crosstalk Avoidance Scheme in VLSI Circuits". International Journal of Computer & organization Trends (IJCOT), V3(2):5-8 Mar - Apr 2013, ISSN:2249-2593, www.ijcotjournal.org. Published by Seventh Sense Research Group.
Abstract
In deep sub micrometer design interconnect delay has become a major factor. Crosstalk is highly evident in deep sub micrometer design. Crosstalk depends on different data patterns that ar e transmitted on the bus. For the avoidance of crosstalk many schemes have been proposed which boost the bus speed or reduce energy consumption. High proportion of the proposed schemes are non linear in nature and are impractical. A crosstalk avoidance cod e which can be implemented practically is dealt with which is based on the representation of numbers in Fibonacci numeral system. An improved version of this scheme is later presented where data is represented in Fibonacci numeral system only if forbidden patterns are present in the data.
References
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Keywords
Codec, crosstalk, Fibonacci number, on - chip bus, deep sub micrometer.