International Journal of Computer
& Organization Trends

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Volume 3 | Issue 2 | Year 2013 | Article Id. IJCOT-V3I4P3 | DOI : https://doi.org/10.14445/22492593/IJCOT-V3I4P3

Redundancy Efficient Crosstalk Avoidance Scheme in VLSI Circuits


Dr. K. Padmapriya , D. Gopinadh

Citation :

Dr. K. Padmapriya , D. Gopinadh, "Redundancy Efficient Crosstalk Avoidance Scheme in VLSI Circuits," International Journal of Computer & Organization Trends (IJCOT), vol. 3, no. 2, pp. 5-8, 2013. Crossref, https://doi.org/10.14445/22492593/ IJCOT-V3I4P3

Abstract

In deep sub micrometer design interconnect delay has become a major factor. Crosstalk is highly evident in deep sub micrometer design. Crosstalk depends on different data patterns that ar e transmitted on the bus. For the avoidance of crosstalk many schemes have been proposed which boost the bus speed or reduce energy consumption. High proportion of the proposed schemes are non linear in nature and are impractical. A crosstalk avoidance cod e which can be implemented practically is dealt with which is based on the representation of numbers in Fibonacci numeral system. An improved version of this scheme is later presented where data is represented in Fibonacci numeral system only if forbidden patterns are present in the data.

Keywords

Codec, crosstalk, Fibonacci number, on - chip bus, deep sub micrometer.

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