Power Efficient Weighted Modulo 2n+1 Adder

Power Efficient Weighted Modulo 2n+1 Adder

  IJCOT-book-cover
 		 International Journal of Computer & Organization Trends (IJCOT)          
 
© 2013 by IJCOT Journal
Volume- 3 Issue- 6                           
Year of Publication : 2013
Authors :  C.Venkataiah , C.Vijaya Bharathi , M.Narasimhulu

Citation

C.Venkataiah , C.Vijaya Bharathi , M.Narasimhulu . "Power Efficient Weighted Modulo 2n+1 Adder" . International Journal of Computer & organization Trends  (IJCOT), V3(6):25-30 Nov - Dec 2013, ISSN 2249-2593, www.ijcotjournal.org. Published by Seventh Sense Research Group.

Abstract

The comparison of three different architectures for modulo 2n +1 adders are introduced in this paper. The first two architecture can be implemented different power consumptions, while maintain the same delay. The partitioned Sklansky structure compared to previous architecture can be implemented less power consumptions, while maintain the different delay and gate counts. The modulo adder 2n +1 adders can be easily derived by adding extra logic of modulo 2 n -1 adder. Power efficient modulo 2n +1 adders are appreciated in a variety of computer applications such as cryptography,RNS. The modulo 2n +1 adder is synthesized using Xilinx 9.1i tool and implemented FPGA spartan2 kit. Keywords Sklansky-style parallel prefix adder, kogge-stone parallel prefix adder, FPGA Spartan 2 kit ,VLSI.

References

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