Power Efficient Weighted Modulo 2n+1 Adder

International Journal of Computer & Organization Trends (IJCOT)          
© 2013 by IJCOT Journal
Volume- 3 Issue- 6                           
Year of Publication : 2013
Authors : C.Venkataiah , C.Vijaya Bharathi , M.Narasimhulu


C.Venkataiah , C.Vijaya Bharathi , M.Narasimhulu . "Power Efficient Weighted Modulo 2n+1 Adder" . International Journal of Computer & organization Trends  (IJCOT), V3(6):25-30 Nov - Dec 2013, ISSN 2249-2593, www.ijcotjournal.org. Published by Seventh Sense Research Group.

Abstract—The comparison of three different architectures for modulo 2n +1 adders are introduced in this paper. The first two architecture can be implemented different power consumptions, while maintain the same delay. The partitioned Sklansky structure compared to previous architecture can be implemented less power consumptions, while maintain the different delay and gate counts. The modulo adder 2n +1 adders can be easily derived by adding extra logic of modulo 2 n -1 adder. Power efficient modulo 2n +1 adders are appreciated in a variety of computer applications such as cryptography,RNS. The modulo 2n +1 adder is synthesized using Xilinx 9.1i tool and implemented FPGA spartan2 kit. Keywords- Sklansky-style parallel prefix adder, kogge-stone parallel prefix adder, FPGA Spartan 2 kit ,VLSI.


[1]. Efficient Weighted Modulo +1 Adders by Partitioned Parallel-Prefix Computation and Enhanced Circular Carry Generation Tso-Bing Juang*, Member, IEEE, Pramod Kumar Meher**, Senior Member, IEEE, and Chin-Chieh Chiu*, 2011.
[2]. T. –B. Juang, C. –C. Chiu and M. –Y. Tsai, “Improved area-efficient weighted modulo +1 adders design with simple correction schemes,”IEEE Transactions on Circuits and Systems II, Exp. Briefs Vol. 57, No.3, pp. 198-202, March 2010.
[3]. H. T. Vergos and C. Efstathiou, “A unifying approach for weighted anddiminished-1 modulo +1 addition,” IEEE Transactions on Circuits and Systems II, Exp. Briefs, Vol. 55, No. 10 , pp. 1041-1045, Oct. 2008.
[4]. H. T. Vergos and D. Bakalis, „„on the use of diminished-1 adders for weighted modulo +1 arithmetic components,‟‟ Proc. 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, pp. 752-759, Sept. 2008.